Week 9

This week we had a lot of problems in defining the interfaces between the frontend and the backend part. From my part, I changed the method of the outputs from parallel to serial in order to communicate with the backend part without problems. 

Moreover, I synthesized the frontend part and from the design there are inferred some latches which cause a lot of timing problems. I changed some of the code and there are only some latches in the color converter which must be fixed.

Also, I created a new version of the frontend part and a new version for the color converter in order to output the data serially.

There are a lot of things to do in the next days:

1) Fix the inferred latches from the design.
2) Create the block buffer module for the frontend part.
3)Complete the encoder.
4)Complete the testbenches for the changed zig zag module and the new color space converter.
5)Write documentation for all the modules.

Week 8

This week passed with a lot of work. The frontend part of the encoder and the zig-zag module merged in the main repository. So, in this stage the frontend part is ready and the backend part of the encoder is missing in order to create the complete JPEG encoder. As discussed with Christopher, I have to write documentation for each module and don't leave it for the last days. Moreover, this week I will try to synthesize each module with different parameters and measure the utilization.

Week 7

The PR with the zig-zag module, is waiting to be merged and reviewed by Christopher. However, a new branch is created which contains the front-end part of the encoder. This part consists of the color-space conversion, dct-2d and zig-zag modules for 8x8 blocks. From a short discussion with Christopher, we decided that hardware utilization with different configurations of the modules should be compute. This will happen the following days.

Week 6

This week merged the 2d-dct and 1d-dct modules into the main repository. Moreover, a new branch (zig-zag) created which contains the zig-zag module and the test units. Christopher re-organized the contributed code and gave us some points to write a more compact style. In the following days, the code will be refactored according to Christopher's recommendations.

Zig-Zag Core

The 2d-dct and 1d-dct modules merged in the main repository by Christopher. Now, it's time for the zig-zag core to be implemented. In the following days I will create a new branch with the zig-zag core and it's unit test.

Extended Modularity and Scalability

Today, I improved my 1d-dct and 2d-dct modules to include NxN blocks transformation. 1D-DCT can convert N vectors and 2D-DCT can convert NxN blocks. There were a lot of issues to deal with.

Firstly, there were some issues when I tried to use list of signals. I intergrated some of the assignments in the interfaces.

Secondly, there were some issues when I tried to use list of interfaces. I had to define some blocks in the code which use the interfaces in order to get converted.

Midterm Evaluation

Midterm evaluation comes this week, so, I will write a little summary of the things that I have done the previous weeks.

As I described in my proposal, the first 3 weeks I implemented the color space conversion module in myhdl. I wrote all the convertible test units (VHDL, MyHDL, and verilog) in order to prove the correct behavior of the module. Moreover, I familiarized with the travis-ci, landscape and coverage tools. I changed some files in the branch to make the travis-ci to work and to increase the coverage and health of my branch. Finally, the branch which I was working there my module got merged in the original repository.

In the 4th week, I experimented with different designs of 2d-dct and chosen a simple and straightforward architecture. In the previous posts, I described the design which I used and the some of the DCT theory. In my working branch of the 2d-dct, I uploaded the module of the 1d-dct with the convertible test-benches. The 1d-dct works fine and it's correct behavior it is shown form the test units and the different tests.

The following days, I will upload the full working 2d-dct module with the respective test units.

As Christopher proposed, we should use a minimal flow for our design and if it is possible to disregard complex FSMs. Thus, the flow in the frontend part of the encoder is kept as minimal as possible. Each pixel is inserted serially in the first module (Color Space Conversion) row by row for each 8x8 block of the image. The outputs of the color space conversion module (Y, Cb, Cr) are inserted parallely in three 2D-DCTs modules and each  of the 2D-DCTs modules after some cycles, outputs parallelly the 8x8 transformed block which consists of 64 signals. The positions of the 64 signals in the 3 8x8 blocks should be changed according to the zig-zag ordering. Then, the  3 blocks are inserted in the backend part for processing.