tag:blogger.com,1999:blog-13748598595311635012024-02-07T21:45:27.307-08:00MyHDL GSOC 2016During the period of the GSoC 2016, I will write weekly posts about my progress in the developing of the frontend part of a JPEG encoder in MyHDL.Anonymoushttp://www.blogger.com/profile/15604495795002581861noreply@blogger.comBlogger24125tag:blogger.com,1999:blog-1374859859531163501.post-64751205335342684952016-08-17T02:46:00.008-07:002016-08-17T14:45:46.670-07:00Work Product
In the following post is summarized the overall work that has been done during the GSoC.
Completed Work
Color Space Conversion Module with parallel inputs and parallel outputs interface
Color Space Conversion Module with serial inputs and serial outputs interface
1D-DCT Module
2D-DCT Module
Zig-Zag Scan Module
Complete Frontend Part of the Encoder
Block Buffer
Input Block Buffer
Anonymoushttp://www.blogger.com/profile/15604495795002581861noreply@blogger.com0tag:blogger.com,1999:blog-1374859859531163501.post-43395352228572240052016-08-17T02:46:00.002-07:002016-08-17T10:23:16.632-07:00Work Product
In the following post is summarized the overall work that has been done during the GSoC.
Completed Work
Color Space Conversion Module with parallel inputs and parallel outputs interface
Color Space Conversion Module with serial inputs and serial outputs interface
1D-DCT Module
2D-DCT Module
Zig-Zag Scan Module
Complete Frontend Part of the Encoder
Block Buffer
Input Block Buffer
Anonymoushttp://www.blogger.com/profile/15604495795002581861noreply@blogger.com0tag:blogger.com,1999:blog-1374859859531163501.post-33080540325386636332016-08-12T02:29:00.001-07:002016-08-12T03:33:05.313-07:00Documentation and Coverage Completed
The coverage, documentation, and synthesis results are in the PR. I am waiting for Chris to review them and tell me what to change.
Anonymoushttp://www.blogger.com/profile/15604495795002581861noreply@blogger.com0tag:blogger.com,1999:blog-1374859859531163501.post-84721592374255892302016-08-08T01:37:00.002-07:002016-08-08T01:37:45.064-07:00Documentation
Today, I start writing the documentation for all of my modules and the complete frontend part. I will use Sphinx. As, the backend is not ready yet, I will try to fill the time by doing this task.
Anonymoushttp://www.blogger.com/profile/15604495795002581861noreply@blogger.com0tag:blogger.com,1999:blog-1374859859531163501.post-53992528494609349252016-08-07T02:02:00.001-07:002016-08-07T02:02:35.079-07:00Week 11
This week I complete the convertible tests for the frontend part and for the new color converter. Vikram, made a PR for the backend part, so the next days we can integrate it with my part and complete the encoder. However, the backend still lacks from complete test coverage with a software prototype. The next days till 15 Augoust which is the end of the coding period I will try to finish the Anonymoushttp://www.blogger.com/profile/15604495795002581861noreply@blogger.com0tag:blogger.com,1999:blog-1374859859531163501.post-73115415515946351992016-07-31T15:16:00.001-07:002016-07-31T15:24:40.378-07:00Block Buffer
Today, I implemented the convertible testbench for the block buffer and the triple_buffer.
The triple buffer has 4 block buffers which store the data from the video source (lines of image) and output then to the frontend part in 8x8 blocks. Each 8x8 block is output three times to the frontend. The video source and the overall design share the same clock. So, in order for the video source Anonymoushttp://www.blogger.com/profile/15604495795002581861noreply@blogger.com0tag:blogger.com,1999:blog-1374859859531163501.post-6823069962845466662016-07-28T10:59:00.002-07:002016-07-28T10:59:08.818-07:00Frontend Synthesis and Block Buffer
This week I managed to eliminate the inferred latches in the design by changing the code. The unexpected latches cause a lot of timing problems. Moreover, I implemented a block buffer which takes each row serially and output a 8x8 block serially in the frontend. This block buffer needs a lot of documentation and a complete convertible testbench.
The following days I will try to complete the Anonymoushttp://www.blogger.com/profile/15604495795002581861noreply@blogger.com1tag:blogger.com,1999:blog-1374859859531163501.post-40243884877844714792016-07-23T01:06:00.000-07:002016-07-23T01:06:01.224-07:00Week 9
This week we had a lot of problems in defining the interfaces between the frontend and the backend part. From my part, I changed the method of the outputs from parallel to serial in order to communicate with the backend part without problems.
Moreover, I synthesized the frontend part and from the design there are inferred some latches which cause a lot of timing problems. I changed some Anonymoushttp://www.blogger.com/profile/15604495795002581861noreply@blogger.com3tag:blogger.com,1999:blog-1374859859531163501.post-35251390252856996532016-07-17T01:19:00.001-07:002016-07-17T01:19:15.677-07:00Week 8
This week passed with a lot of work. The frontend part of the encoder and the zig-zag module merged in the main repository. So, in this stage the frontend part is ready and the backend part of the encoder is missing in order to create the complete JPEG encoder. As discussed with Christopher, I have to write documentation for each module and don't leave it for the last days. Moreover, this week Anonymoushttp://www.blogger.com/profile/15604495795002581861noreply@blogger.com0tag:blogger.com,1999:blog-1374859859531163501.post-27867943638273206742016-07-10T05:05:00.001-07:002016-07-10T05:05:17.818-07:00Week 7
The PR with the zig-zag module, is waiting to be merged and reviewed by Christopher. However, a new branch is created which contains the front-end part of the encoder. This part consists of the color-space conversion, dct-2d and zig-zag modules for 8x8 blocks. From a short discussion with Christopher, we decided that hardware utilization with different configurations of the modules should be Anonymoushttp://www.blogger.com/profile/15604495795002581861noreply@blogger.com0tag:blogger.com,1999:blog-1374859859531163501.post-14082405955702623262016-07-03T14:19:00.000-07:002016-07-03T14:19:08.055-07:00Week 6
This week merged the 2d-dct and 1d-dct modules into the main repository. Moreover, a new branch (zig-zag) created which contains the zig-zag module and the test units. Christopher re-organized the contributed code and gave us some points to write a more compact style. In the following days, the code will be refactored according to Christopher's recommendations.
Anonymoushttp://www.blogger.com/profile/15604495795002581861noreply@blogger.com0tag:blogger.com,1999:blog-1374859859531163501.post-29282242308372218342016-07-01T00:44:00.002-07:002016-07-01T00:44:47.873-07:00Zig-Zag Core
The 2d-dct and 1d-dct modules merged in the main repository by Christopher. Now, it's time for the zig-zag core to be implemented. In the following days I will create a new branch with the zig-zag core and it's unit test.
Anonymoushttp://www.blogger.com/profile/15604495795002581861noreply@blogger.com0tag:blogger.com,1999:blog-1374859859531163501.post-71954247887954538742016-06-26T10:25:00.003-07:002016-06-26T10:25:33.206-07:00Extended Modularity and Scalability
Today, I improved my 1d-dct and 2d-dct modules to include NxN blocks transformation. 1D-DCT can convert N vectors and 2D-DCT can convert NxN blocks. There were a lot of issues to deal with.
Firstly, there were some issues when I tried to use list of signals. I intergrated some of the assignments in the interfaces.
Secondly, there were some issues when I tried to use list of interfaces. I Anonymoushttp://www.blogger.com/profile/15604495795002581861noreply@blogger.com0tag:blogger.com,1999:blog-1374859859531163501.post-83880337781466549312016-06-19T07:35:00.000-07:002016-06-19T07:35:36.455-07:00Midterm Evaluation
Midterm evaluation comes this week, so, I will write a little summary of the things that I have done the previous weeks.
As I described in my proposal, the first 3 weeks I implemented the color space conversion module in myhdl. I wrote all the convertible test units (VHDL, MyHDL, and verilog) in order to prove the correct behavior of the module. Moreover, I familiarized with the travis-ci, Anonymoushttp://www.blogger.com/profile/15604495795002581861noreply@blogger.com0tag:blogger.com,1999:blog-1374859859531163501.post-4535582605143480752016-06-19T02:59:00.000-07:002016-06-19T02:59:11.188-07:002D-DCT Part 2
Now, I think it's time to present in details the implementation of the 2d-dct.
In the previous post, I described that I used the row-column decomposition approach which uses two 1d-dcts and utilizes the following equation: Z=A*X*AT. The first 1d-dct takes each input serially and outputs the 8 signal vector parallely and implements the following equation: Y = A * XT. X is the Anonymoushttp://www.blogger.com/profile/15604495795002581861noreply@blogger.com0tag:blogger.com,1999:blog-1374859859531163501.post-72266472179042123552016-06-15T13:01:00.001-07:002016-06-18T00:18:13.704-07:002D-DCT Part 1
The forward 2D-DCT is computed from the following equation:
In the previous equation N is the block size, in our situation our block size is 8x8 so N=8, x(i, j) is the input sample and X(m,n) is the dct transformed matrix.
A straightforward implementation of the previous equation requires N4 multiplications. However, the DCT is a separable transform and it can be expressed in Anonymoushttp://www.blogger.com/profile/15604495795002581861noreply@blogger.com4tag:blogger.com,1999:blog-1374859859531163501.post-57543204304569740892016-06-13T13:43:00.001-07:002016-06-13T13:43:45.670-07:002D-DCT Implementation
The third week passed, and the color space conversion module with the unit tests merged in the original repository.
These days, I figured out how to implement the 2D-DCT with a simple and straightforward way. The implementation follows the row-column decomposition method.
First I created and tested the 1D-DCT module and then I created and tested the final 2D-DCT module. In the following Anonymoushttp://www.blogger.com/profile/15604495795002581861noreply@blogger.com0tag:blogger.com,1999:blog-1374859859531163501.post-63022248726622414352016-06-09T11:02:00.000-07:002016-06-09T11:02:39.167-07:00Created separate tests and improved code quality
As Chris pointed, I split the original test unit into two separate tests. The first test checks the color conversion module with myhdl simulator while the second test checks the outputs of the converted testbench in Verilog and VHDL with the outputs of the myhdl simulator.
Moreover, I improved the code quality of the rgb2ycbcr.py in order to increase the health of the module using landscape.io
Anonymoushttp://www.blogger.com/profile/15604495795002581861noreply@blogger.com0tag:blogger.com,1999:blog-1374859859531163501.post-22077747741609658702016-06-04T11:35:00.002-07:002016-06-04T11:35:53.981-07:00Code Refactoring
Till to this day, I refactored all the code which I have submitted in the previous commits. As Christopher Felton showed me, the code for the color space conversion and the test-benches refactored accordingly. However, there are still some changes to be made in order for the code of the test unit to be more readable. I created a different branch which I edit there my reworked Anonymoushttp://www.blogger.com/profile/15604495795002581861noreply@blogger.com0tag:blogger.com,1999:blog-1374859859531163501.post-74705846075631703312016-05-30T12:36:00.000-07:002016-05-30T12:36:57.656-07:00A lot of changes should be made
Today Chrisopher checked my pull request as regards the color space conversion module.
The PR can be found here:
https://github.com/mkatsimpris/test_jpeg/pull/3#discussion_r65075717
The main issues that must be fixed are:
PEP8 code refactoring
Interfaces change (add enable_in as data_valid in interfaces)
Add docstring comments in interfaces and in blocks
Add a comment Anonymoushttp://www.blogger.com/profile/15604495795002581861noreply@blogger.com0tag:blogger.com,1999:blog-1374859859531163501.post-77595873109009208492016-05-28T11:21:00.001-07:002016-05-28T11:21:46.158-07:00Make more tests
Today, Christopher point me some changes to do in my code in the pull requests in order to make my module more. I made these minor changes and I will wait for more feedback in order to improve my code in terms of scalability, modularity, and readability. When all the changes implemented the pull request will finally be merged in the original repository.
Meanwhile, I run some tests of the Anonymoushttp://www.blogger.com/profile/15604495795002581861noreply@blogger.com0tag:blogger.com,1999:blog-1374859859531163501.post-88059731745081258812016-05-27T00:29:00.002-07:002016-05-27T00:29:31.940-07:00Implementing the Color Space conversion module
In this week my responsibilities are to understand how the color space conversion module works and write a test unit for the module. However I moved a bit ahead. I implemented the module and the test unit in myhdl.
Firstly, I read a lot of material to understand how the conversion from rgb to luminance and chrominance works. The equations which used in the conversion are:
Y = (0.299*R)+(Anonymoushttp://www.blogger.com/profile/15604495795002581861noreply@blogger.com0tag:blogger.com,1999:blog-1374859859531163501.post-16843575521812595242016-05-22T02:50:00.001-07:002016-05-22T02:53:51.818-07:00GSoC Community Bonding Period
Good news! My proposal got accepted from Python Software Foundation for GSoC 2016. I will be working on MyHDL sub-organization writing code from 23 May till 23 August.
The main goal of the proposed project is to create the frontend part of a JPEG encoder which will be implemented in MyHDL. The frontend part consists of the color-space converter, the 2D DCT, the top-level FSM, and the input Anonymoushttp://www.blogger.com/profile/15604495795002581861noreply@blogger.com0tag:blogger.com,1999:blog-1374859859531163501.post-20746874826212642772016-03-12T02:28:00.003-08:002016-03-13T04:18:27.816-07:00First Post
From this simple first post starts the fascinating ride through the exciting world of GSoC 2016. If I get accepted to participate in GSoC 2016, the organization I will be working, is called MyHDL and more details can be found in http://myhdl.org.
Anonymoushttp://www.blogger.com/profile/15604495795002581861noreply@blogger.com0