In the following post is summarized the overall work that has been done during the GSoC.
- Color Space Conversion Module with parallel inputs and parallel outputs interface
- Color Space Conversion Module with serial inputs and serial outputs interface
- 1D-DCT Module
- 2D-DCT Module
- Zig-Zag Scan Module
- Complete Frontend Part of the Encoder
- Block Buffer
- Input Block Buffer
All the above modules except 7 and 8 are merged in the main repository. Each module is verified for it's correct behavior with a software reference and additional MyHDL and vhdl/verilog convertible testbenches created for each module. All the modules are modular and scalable in terms of the NxN blocks which they can process and the fractional bits for the fixed point computations which they can handle. The documentation for the overall project is here and could be created using make html. Also, the documentation can be seen online here.The documentation includes the description for each module, interface, testbench and additionally the coverage results for each module and the synthesis results for the complete frontend part.
- My working fork: https://github.com/mkatsimpris/test_jpeg
- Main Repository: https://github.com/cfelton/test_jpeg
- List of all the PRs before and during the GSoC:
- List of all PRs in the main repo: here