Implementing the Color Space conversion module

In this week my responsibilities are to understand how the color space conversion module works and write a test unit for the module. However I moved a bit ahead. I implemented the module and the test unit in myhdl.

Firstly, I read a lot of material to understand how the conversion from rgb to luminance and chrominance works. The equations which used in the conversion are:

Y = (0.299*R)+(0.587*G)+(0.114*B)

Cb = (-0.1687*R)-(0.3313*G)+(0.5*B)+128

Cr = (0.5*R)-(0.4187*G)-(0.0813*B)+128

 As we can see from the above equation the coefficients in the multiplication are  number that are smaller than 1. The hardware implementation of the coefficients will be a fixed point 2s complement representation. In fixed point representation must be specified the format of the representation by specifying the integer bits, fractional bits, and sign bit. However in this equation all the numbers are below 1 so we have no integer bit, only fractional bits and sign bit. The implemented module will be scalable with respect to the specified fractional bits, and the coefficients.

 In my first attempt to implement the module and the test-bench I faced some issues which I will describe in the next paragraphs.

1) Bad conversion of the myhdl test-bench to verilog code. There is an issue in myhdl with the assignment of negative numbers from a list to a signal. The bug can be seen in this gist: https://gist.github.com/mkatsimpris/6490baf7e76e054f76880da3fabb2e65.

2) The code written in myhdl must respect each languages (VHDL, verilog) peculiarities. When I wrote the code of the module and the test unit in myhdl everything worked fine. The output values of my module (Y, Cr ,Cb) were correct with comparison to a software implementation of the color space converter. However when I tried to verify the converted test-bench in verilog everything failed. The reason was that I didn't account how the verilog handles the 2s complement operations. There is an example: (a*-b) and -(a*b) give different outputs in verilog. The correct is -(a*b) in order to handle the output like 2s complement. So some changes should be done in myhdl code in order to pass the convertion and verification test.

In order to solve all of the above issues I will verify the conversion and the correct output of the test units in VHDL with the help of GHDL instead of using verilog and iverilog.