Sunday, May 22, 2016

GSoC Community Bonding Period

Good news! My proposal got accepted from Python Software Foundation for GSoC 2016. I will be working on MyHDL sub-organization writing code from 23 May till 23 August.

The main goal of the proposed project is to create the frontend part of a JPEG encoder which will be implemented in MyHDL. The frontend part consists of the color-space converter, the 2D DCT, the top-level FSM, and the input buffer. Based on a reference design, the final implementation in MyHDL will provide a more modular and scalable design. Throughout the project, will be developed all the required unit tests to prove the correct functionality of each block of the frontend part of the encoder while keeping in mind not only to verify the correct behavior of the design but also to produce synthesizable VHDL/Verilog code. The ideal goal would be to create a fully working JPEG encoder by combining the frontend and the backend part of the encoder written in MyHDL and implement the converted code in a FPGA board in order to measure some metrics like resource utilization and performance.

As regards the community bonding period, me and Nikolaos Kavvadias my supervisor, arranged some Skype calls in order to discuss some issues about the proposal and get to know each other. Nikolaos gave me a lot of useful advises and pointed me the right directions to start designing each module. His experience and help are appreciated and I think that we will have a great time during the project.

During the community bonding period some helpful advises were given from the guys in the IRC channel which get me unstuck in some problems I had with MyHDL. Christopher Felton is online 24/7 in the channel and provides really useful help as regards MyHDL issues and general hardware issues about the project.

In the following paragraphs I will give some short details about each module which I will design in the frontend part of the JPEG encoder.

General System Architecture

The image is taken from the documentation of the reference design which will be used during the project http://opencores.org/project,mkjpeg.

Buffer Fifo Module
 
Host Data interface writes input image line by line to BUF_FIFO. This FIFO is intended to minimize latency between raw image loading and encoding start. It performs raster to block conversion (line wise input to 8x8 block conversion). BUF_FIFO is actually a RAM. BUF_FIFO must be able to store at least 8 lines of input image, so that JPEG encoding can be started for 8x8 blocks.  


RGB to YCbCr Module 

Following equation is implemented by means of multipliers and adders to perform conversion:


Y = (0.299*R)+(0.587*G)+(0.114*B)
Cb = (-0.1687*R)-(0.3313*G)+(0.5*B)+128
Cr = (0.5*R)-(0.4187*G)-(0.0813*B)+128

Constants used in this equation have format 14 bits of precision plus 1 sign bit on MSB. 

FDCT 

FDCT is intended to perform functions: RGB to YCbCr conversion, chroma subsampling, input level shift and 2D DCT (discrete cosine transform).

Zig Zag


Zig-Zag block is responsible to perform so called zig-zag scan. It is simply reorder of samples positions in one 8x8 block according to following tables. 

input order (natural):

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
...
...





































...
...
62
63

Zig-zag output order:

0
1
5
6
14
15
27
28
2
4
7
13
16
26
29
42
3
8
12
17
25
30
41
43
9
11
18
24
31
40
44
53
10
19
23
32
39
45
52
54
20
22
33
38
46
51
55
60
21
34
37
47
50
56
59
61
35
36
48
49
57
58
62
63

It means for example that first sample (position 0) is mapped to the same output position 0. Sample 2 is mapped to output position 5, etc.

Control State Machine

Control State Machine is an FSM which will control the whole encoding process.

 




 


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